Workshop : Challenges in Compiling for Scalable Parallel Systems

Santosh Pande <>
17 Sep 1996 00:15:51 -0400

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Workshop : Challenges in Compiling for Scalable Parallel Systems (Santosh Pande) (1996-09-17)
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From: Santosh Pande <>
Newsgroups: comp.compilers
Date: 17 Sep 1996 00:15:51 -0400
Organization: Compilers Central
Keywords: conference, parallel

A workshop on `Challenges in Compiling for Scalable Parallel Systems'
will be conducted as a part of the 8th IEEE Symposium on Parallel
and Distributed Processing (SPDP '96) on October 24th at New Orleans, LA.

The advance program of the workshop is enclosed below. For more details
on the technical program, please contact:

Prof. Santosh Pande
Department of ECECS
PO Box 210030
University of Cincinnati
Cincinnati, OH 45221-0030

Phone : (513) 556 4785
Fax : (513) 556 7326

For registration information, please contact:

Prof. Behrooz Shirazi
Dept. of Computer Science and Engineering
University of Texas at Arlington
Box 19015
Arlington, TX 76019-0015

Phone : (817) 272-3605
Fax : (817) 272-3784

Register before October 7th to get a discount!


Workshop on
        Challenges in Compiling for Scalable Parallel Systems

        Organizers: Santosh Pande (Univ. Cincinnati), J. Ramanujam (LSU)
                                              and Yves Robert (ENS, Lyon, France)

                        Date : Thursday, October 24th 1996.


                                                    Advance Program


Opening remarks : Santosh Pande, J. Ramanujam and Yves Robert : 8:30 am

Session I : Communication Analysis and Optimization (8:30 am
to 10:00 am):
The theme of this session
is to address the crucial problem of
analyzing and optimizing communication through interprocedural dataflow analysis
or loop iteration and data space partitioning using linear algebra.

1. Rajiv Gupta, University of Pittsburgh, ``Demand Driven Dataflow
Analysis for Communication Optimizations''
2. Yves Robert, LIP, ENS-Lyon, ``Optimizing Residual Communication through
3. Panel discussion of speakers and question/answers.

Coffee Break : 10:00 am to 10:30 am.

Session II : Data layout (10:30 am to 12:00 noon) : Efficient
data layouts are essential elements of exploiting data parallelism.
This session presents static and dynamic techniques for automatic
data partitioning and layout.

1. Uli Kremer, Rutgers, ``Automatic Data Layout using 0-1
Integer Programming''
2. Prithviraj Banerjee andi D. Palermo, Northwestern, ``Dynamic Data
Partitioning in Distributed Memory Multicomputers''
3. Panel discussion of speakers and question/answers.

Lunch Break : 12:00 noon to 1:00 pm

Session III : Granularity and Tiling (1:00 pm to 3:30 pm):
The importance of tiling is
increasing, as programming distributed memory machines require a large grain
size to be efficient. The link with fully permutable loop nests is also

1. Alain Darte, ENS Lyon, France, ``Tiling Fully Permutable Loop Nests''
2. J. Ramanujam, Louisiana State University, ``Tiling for Locality''.
3. Boleslaw Szymanski, Rensselaer Polytechnic Institute, ``Loop
Tiling for Parallel Execution''
4. Jingling Xue, University of New England, Australia, ``Time-optimal
Tiling of Uniform Dependence Loops''
5. Panel discussion of speakers and question/answers.

Coffee break : 3:30 pm to 4:00 pm

Session IV : Languages and Systems (4:00 pm to 5:15 pm):
Recent language/system efforts
focus on efficiently supporting data and task parallelism aiming for
a high degree of automating the compilation process. This session seeks
to focus on such specific efforts and their impact on future research.

1. Rob Schreiber, HP Labs, "HPF 2.0"
2. David Padua and Y. Paek, UIUC, "Compiling for Scalable Multiprocessors
with Polaris"
3. Panel discussion of speakers and question/answers.


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