Re: Compile HLL to microcode on VLIW - possible?

doconnor@sedona.intel.com (Dennis O'Connor~)
20 Apr 1996 23:45:45 -0400

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Related articles
[4 earlier articles]
Re: Compile HLL to microcode on VLIW - possible? narad@nudibranch.asd.sgi.com (1996-04-10)
Re: Compile HLL to microcode on VLIW - possible? preston@tera.com (1996-04-11)
Re: Compile HLL to microcode on VLIW - possible? narad@nudibranch.asd.sgi.com (1996-04-13)
Re: Compile HLL to microcode on VLIW - possible? preston@tera.com (1996-04-16)
Re: Compile HLL to microcode on VLIW - possible? krste@ICSI.Berkeley.EDU (1996-04-18)
Re: Compile HLL to microcode on VLIW - possible? andy@Xenon.Stanford.EDU (1996-04-18)
Re: Compile HLL to microcode on VLIW - possible? doconnor@sedona.intel.com (1996-04-20)
Re: Compile HLL to microcode on VLIW - possible? WStreett@shell.monmouth.com (1996-04-29)
Re: Compile HLL to microcode on VLIW - possible? alaric@abwillms.demon.co.uk (Alaric B. Williams) (1996-04-29)
Re: Compile HLL to microcode on VLIW - possible? bill@amber.ssd.hcsc.com (1996-04-30)
Re: Compile HLL to microcode on VLIW - possible? ok@cs.rmit.edu.au (1996-05-01)
Re: Compile HLL to microcode on VLIW - possible? Arthur.Chance@Smallworld.co.uk (1996-05-02)
Re: Compile HLL to microcode on VLIW - possible? alaric@abwillms.demon.co.uk (Alaric B. Williams) (1996-05-03)
[2 later articles]
| List of all articles for this month |

From: doconnor@sedona.intel.com (Dennis O'Connor~)
Newsgroups: comp.compilers,comp.arch
Date: 20 Apr 1996 23:45:45 -0400
Organization: Intel Corporation, Chandler, AZ
References: 96-04-059 96-04-094 96-04-109
Keywords: architecture, performance, comment

Preston Briggs <preston@tera.com> wrote:
>And that's the whole deal. With instruction caches, you can make the
>hardwired instruction cycle as fast as microcode. There's no reason
>to have a separate level of instruction interpretation.


andy@Xenon.Stanford.EDU (Andy Freeman) writes:
] That assumes that the only purpose of microcode is sequencing and
] composition. While sequencing is the mechanism, is it really the only
] worthwhile purpose? (Given the PALcode example, protected sequencing
] isn't a microcode exclusive.) I can't think of others, but ....


Imagine an era where logic/processor speeds are outstripping memory
speed. A compactly coded instruction set will lead to a lower I-cache
miss rate from a fixed size cache or the same per-instruction miss
rate from a smaller cache. The gain from either of these may easily
justify the cost of complex decoding and/or microcoded execution.


Or, in buzzword, CISC may help when we hit the memory wall.


This is an example of why many believe there is no "best architecture"
: the underlying implementation technology keeps changing, and this
changes which architectures can be efficiently executed at high speed.
--
Dennis O'Connor doconnor@sedona.intel.com
[Are we swinging back to a slow memory era again? Considering how hard
people are working on cache designs, I guess so. -John]
--


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