Re: Compile HLL to microcode on VLIW - possible?

krste@ICSI.Berkeley.EDU (Krste Asanovic)
18 Apr 1996 00:32:11 -0400

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Related articles
[2 earlier articles]
Re: Compile HLL to microcode on VLIW - possible? kim@jrs.com (Kim Whitelaw) (1996-04-08)
Re: Compile HLL to microcode on VLIW - possible? aaedonnelly@voyager.net (Donnelly) (1996-04-10)
Re: Compile HLL to microcode on VLIW - possible? narad@nudibranch.asd.sgi.com (1996-04-10)
Re: Compile HLL to microcode on VLIW - possible? preston@tera.com (1996-04-11)
Re: Compile HLL to microcode on VLIW - possible? narad@nudibranch.asd.sgi.com (1996-04-13)
Re: Compile HLL to microcode on VLIW - possible? preston@tera.com (1996-04-16)
Re: Compile HLL to microcode on VLIW - possible? krste@ICSI.Berkeley.EDU (1996-04-18)
Re: Compile HLL to microcode on VLIW - possible? andy@Xenon.Stanford.EDU (1996-04-18)
Re: Compile HLL to microcode on VLIW - possible? doconnor@sedona.intel.com (1996-04-20)
Re: Compile HLL to microcode on VLIW - possible? WStreett@shell.monmouth.com (1996-04-29)
Re: Compile HLL to microcode on VLIW - possible? alaric@abwillms.demon.co.uk (Alaric B. Williams) (1996-04-29)
Re: Compile HLL to microcode on VLIW - possible? bill@amber.ssd.hcsc.com (1996-04-30)
Re: Compile HLL to microcode on VLIW - possible? ok@cs.rmit.edu.au (1996-05-01)
[4 later articles]
| List of all articles for this month |

From: krste@ICSI.Berkeley.EDU (Krste Asanovic)
Newsgroups: comp.compilers,comp.arch
Date: 18 Apr 1996 00:32:11 -0400
Organization: International Computer Science Institute, Berkeley, CA, U.S.A.
References: 96-04-059 96-04-083 96-04-094
Keywords: architecture

preston@tera.com (Preston Briggs) writes:
|> And that's the whole deal. With instruction caches, you can make the
|> hardwired instruction cycle as fast as microcode. There's no reason
|> to have a separate level of instruction interpretation.


True.


However you can build flash (or ordinary) ROM, much denser than SRAM.
In fact much denser than even DRAM theoretically since you don't need
the storage capacitor. I'm not sure of the exact SRAM:ROM area ratio,
maybe around 8:1?


Many cheap microcontrollers and DSPs have large chunks of ROM, with
some even having flash ROM on chip (e.g., the new TMS320F206&7 DSPs
will have 64KB of flash ROM on board).


Of course, it's difficult to make a case for say 32KB of L1 flash ROM
alongside the L1 instruction cache in a general purpose system. Are
any routines so important they're worth embedding at the L1 level?
Either to reduce total L1 miss penalties, or reduce worst-case
latencies?


--
Krste Asanovic phone: +1 (510) 642-4274 x143
International Computer Science Institute fax: +1 (510) 643-7684
1947 Center Street, Suite 600 email: krste@icsi.berkeley.edu
Berkeley, CA 94704-1198, USA http://www.icsi.berkeley.edu/~krste


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