Call for Papers: Micro-29 (Paris, 12/96) (steve beaty)
10 Apr 1996 08:34:01 -0400

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Call for Papers: Micro-29 (Paris, 12/96) (1996-04-10)
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From: (steve beaty)
Newsgroups: comp.compilers,comp.arch,comp.parallel
Date: 10 Apr 1996 08:34:01 -0400
Organization: Colorado State University, Fort Collins, CO 80523
Keywords: conference, CFP, parallel, architecture

                                                                CALL FOR PAPERS


                                                      THE 29th ANNUAL IEEE/ACM

                                                      with special emphasis on
                                          Instruction-Level Parallel Processing

                                                                  Paris, France
                                                          December 2 - 4, 1996

                                                                Co-sponsored by
                                              IEEE TC-MICRO and ACM SIGMICRO

                                                              Important dates:
              SUBMISSION: JUNE 14 Acceptance: AUG. 16 Final version: SEPT. 13

The Microarchitecture Symposia have become a premier forum in
recent years, combining high-quality research in fields that include
instruction-level parallelism (ILP), compilers, and architectures.
In the quest for increased performance, industry and academia have been
focusing more on ILP. New techniques are being developed to extract higher
levels of parallelism with ILP compilers and architectures. The goals of
this conference are to bring together researchers in fields related to
instruction-level parallelism, to encourage interaction, and to further
the state of the art in microarchitectures and fine-grain parallel
processing. Papers are solicited in fields including the following:

* Compiler techniques for instruction-level parallelism: software pipelining,
                global scheduling, register allocation, memory disambiguation,
                novel optimizations.
* Theoretical foundations of instruction level parallelism.
* ILP architectures and designs: VLIW, superscalar, multiscalar, ...
* Object code translation.
* Branch prediction hardware and software.
* Compiler and hardware techniques for improving memory system performance.
* Application of ILP techniques to Design Automation.
* Parallel algorithms for fine grain parallel architectures.

THE DEADLINE FOR SUBMISSIONS IS JUNE 14, 1996. Please submit one
electronic copy of a paper (in PostScript format) not longer than
5000 words. For instructions on how to submit, please send email to: or read the instructions on the Web page: Notification of acceptance will occur by August
16, 1996. The camera ready copy of the accepted papers will be due on
September 13, 1996. In order to minimize problems with your electronic
submissions please ensure your postscript submission can be previewed
by Ghostview. Contact with any questions.


Steve Beaty, Hewlett-Packard
Steve Melvin, Zytek

Local Arrangements
Ulrich Finger

Steering Committee
Richard Belgard, Consultant Wen-mei Hwu, UIUC
James Bondi, Texas Instruments Gearold Johnson, NTU
Matthew Farrens, UC Davis Yale Patt, U. Michigan
Stan Habib, CUNY Andrew Wolfe, Princeton

Program Committee
Vicki Allan, Utah State Wen-mei Hwu, UIUC
Richard Belgard, Consultant Gearold Johnson, NTU
David Bernstein, IBM Haifa Daniel Litaize, IRIT
Jim Bondi, Texas Instruments Bill Mangione-Smith, UCLA
Steve Carr, Michigan Tech Trevor Mudge, U. Michigan
Tom Conte, NC State Yale Patt, U. Michigan
Henk Corporaal, Delft Bob Rau, HP Labs
Edward Davidson, U. Michigan Uwe Schwiegelshohn, Dortmund
Jim Dehnert, Silicon Graphics Andre Seznec, IRISA
Kemal Ebcioglu, IBM Watson Jim Smith, U. Wisconsin
Christine Eisenbeis, INRIA Mike Smith, Harvard
Daniel Etiemble, Mark Smotherman, Clemson
Paolo Faraboschi, HP Labs Guri Sohi, U. Wisconson
Matthew Farrens, UC Davis Phil Sweany, Michigan Tech
Stephan Freudenberger, HP Labs Gary Tyson, UC Riverside
Guang Gao, McGill Andrew Wolfe, Princeton
Andy Glew, Intel Tse-Yu Yeh, Intel
Stanley Habib, CUNY


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