Re: the RISC penalty (Peter Klausler)
31 Dec 1995 12:05:40 -0500

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From: (Peter Klausler)
Newsgroups: comp.compilers
Date: 31 Dec 1995 12:05:40 -0500
Organization: at home in Minneapolis
References: 95-12-132 95-12-154 95-12-156
Keywords: architecture

Michael Meissner wrote:
>Well it depends on how you view the instruction stream. True variable
>sized nstructions are a pain, but did it in terms of 60-bit words (ie,
>instructions would not cross a word boundary, so if you wanted to use a
>30-bit instruction, and there are only 15 bits left in the word, you have
>to put a NOP, and start on the next word). writes:
>This was true of the lower-end machines, but was NOT true of the 6600 and
>higher machines. They had the 8-word instruction stack (a microscopic
>instruction fetch cache), and could handle 30-bit instructions that spanned
>word boundaries.

Just for historical accuracy: the instruction stack was indeed 8 words, but
one of them held the "next instruction word" fetched from after the loop,
so the challenge was to squeeze the code into SEVEN words. There was a
library called STACKLIB containing routines thus optimized.

Also, the 6600, etc., used word addresses to address code, so the
assembler had to insert NOPs (inst 046) to "force upper" before
labels to get them properly aligned.

Sigh. Programmers never get to have this much fun any more.
Puzzling out multiple inheritance just doesn't compare. :-)

Source: Assembly Language Programming for the Control Data 6000
and Cyber Series by Grishman, a wonderful book, dedicated to A6
and A7, "without which none of the results in this book could
have been saved."

Peter Klausler ( "They're beating my head against a dead horse."

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