Re: Reuse of computations

citron@CS.HUJI.AC.IL (Daniel Citron) writes:


>I'm interested in papers that refer to the reuse of previously executed
>computations. I think the term is memoing or memoizing. Are there any
>practical >implementations of this concept (in software or hardware)?




I'm not sure if this is the type of thing you are looking for or not,
but the following reference presents a register allocation technique
that relies on the ability re-compute a value based on previously
executed computations that are still in the register file (as opposed
to using a spill/reload sequence):


@inproceedings{Briggs92,
      AUTHOR = {P. Briggs and K. Cooper and L. Torczon},
      BOOKTITLE = pldi,
      TITLE = {Rematerialization},
      YEAR = {1992}
}


Alex Nicolau and I also published a paper last year on integrating
code selection, register allocation, and instruction scheduling into
a unified framework, that makes even more aggressive use of
previously computed values. I've included a reference and the
abstract below, if you are interested. The full text of the paper
can be found in Postscript format at the URL:


      http://www.ics.uci.edu/~snovack/papers/ms/ms.ps


Cheers,
Steve


@incollection{Novack94,
          AUTHOR = {S. Novack and A. Nicolau},
          BOOKTITLE = {Languages and Compilers for Parallel Computing},
          SERIES = {Lecture Notes in Computer Science},
          VOLUME = {892},
          PUBLISHER = {Springer-Verlag},
          TITLE = {Mutation Scheduling: A Unified Approach to Compiling
for Fine-Grain Parallelism},
          ABSTRACT = {


          Trade-offs between code selection, register allocation, and instruction
          scheduling are inherent to compiling for fine-grain parallel
          architectures, but the conventional approach to compiling for such
          machines arbitrarily separates these phases so that decisions made
          during any one phase place unnecessary constraints on the remaining
          phases. Mutation Scheduling attempts to solve this problem by
          combining code selection, register allocation, and instruction
          scheduling into a unified framework in which trade-offs between the
          functional, register, and memory bandwidth resources of the target
          architecture are made ``on the fly'' in response to changing resource
          constraints and availability.


          },
          YEAR = {1994}
}
--

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