|Optimizing assembler for SPARC Xavier.Leroy@inria.fr (Xavier Leroy) (1994-08-01)|
|Re: Optimizing assembler for SPARC firstname.lastname@example.org (Mark Leone) (1994-08-02)|
|Re: Optimizing assembler for SPARC email@example.com (Mark Leone) (1994-08-03)|
|From:||Mark Leone <firstname.lastname@example.org>|
|Organization:||School of Computer Science, Carnegie Mellon|
|Date:||Wed, 3 Aug 1994 18:43:11 GMT|
Mark Leone <email@example.com> wrote:
>Beware: the MIPS assembler has similar problems. It assumes that the
>so-called temporary registers ($t0-$t9) are never live across procedure
>Is there a way to defeat this behavior (other than .set nomove)? Are
>there any "general purpose" MIPS schedulers out there?
Michael Meissner pointed me in the right direction: later versions of
the MIPS assembler (e.g. 2.1) provide a ".livereg" directive that is
documented in Kane and Heinrich's 1992 architecture reference:
.livereg indicates to the assembler which registers are live
before a jump, to avoid unsafe optimizations by the
reorganizer. The directive .livereg takes two arguments,
int_bitmask, and fp_bitmask, which are 32-bit bitmasks with a
bit turned on for each register that is live before a jump.
The most significant bit (!) corresponds to register $0....
Mark Leone <firstname.lastname@example.org>
School of Computer Science, Carnegie Mellon University
Pittsburgh, PA 15213 USA
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