|Target machine for compiler course Mike.Spivey@comlab.oxford.ac.uk (1994-06-01)|
|Re: Target machine for compiler course firstname.lastname@example.org (Marc Brandis) (1994-06-03)|
|Re: Target machine for compiler course email@example.com (Andrew Tucker) (1994-06-03)|
|Re: Target machine for compiler course firstname.lastname@example.org (1994-06-03)|
|Re: Target machine for compiler course email@example.com (1994-06-03)|
|Re: Target machine for compiler course firstname.lastname@example.org (1994-06-11)|
|Re: Target machine for compiler course email@example.com (1994-06-05)|
|Re: Target machine for compiler course firstname.lastname@example.org (1994-06-13)|
|[2 later articles]|
|From:||Marc Brandis <email@example.com>|
|Organization:||Dept. Informatik, Swiss Federal Institute of Technology (ETH), Zurich, CH|
|Date:||Fri, 3 Jun 1994 11:47:33 GMT|
Mike Spivey <Mike.Spivey@comlab.oxford.ac.uk> wrote:
>It might be nice to generate code for the SPARCstations that my
>students will use for their practicals. But isn't generating code for
>RISC machines with register windows, delay slots, etc. too much for a
>first detailed look?
We have been using real machines as targets in our compiler construction
courses at ETH Zurich with very good success. In our case, it was the NS32000,
the M680x0, and the i386.
As long as you do not attempt to many optimizations, and ignore some special
properties of an architecture, it is not that much harder than for a
hypothetical machine. When you use a hypothetical machine, you abstract from
special properties, and you can just as well do this with a real architecture,
as long as it is regular enough for your course.
I personally think the SPARC would be a nice target. It has a small and
regular instruction set. Register windows are not that hard to explain. You
could ignore the presence of delay slots in the beginning, and maybe deal with
this at the end of the course and let the students build a simple basic-block
scheduler taking care of delay slots as well. In order to make use of
registers, you could use 'register' declarations, or use a simple heuristic.
In order not to have to deal with the pretty complex calling convention, you
could restrict the parameter list so that everything can be passed in
registers. As a whole, I do not think it would be harder than for the
processors we have been using.
Being able to run their generated code is a great experience for the students.
>Or maybe we should generate code for the 8086, then some students will
>be able to run the code at home.
In my opinion, the 8086 is too irregular to make a good target for a course.
If you target the 386 in a flat 32-bit model, it becomes much better.
Institute for Computer Systems
ETH-Zentrum (Swiss Federal Institute of Technology)
CH-8092 Zurich, Switzerland
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