|PowerPC Tools firstname.lastname@example.org (1994-06-01)|
|PowerPC Tools email@example.com (1994-06-17)|
|Organization:||IBM Advanced Workstation Division|
|Date:||Wed, 1 Jun 1994 22:11:05 GMT|
I'm an architect for a software development toolset IBM is planning in
support of our PowerPC chips. The intended audience for the toolset would
be compiler/assembler writers, operating systems developers, performance
analysts, and system designers.
If you fall into one of the above camps (directly or indirectly), I'd
appreciate your opinions as to what kinds of tools and documentation you'd
like to have us (IBM) provide you to make your life easier for the PowerPC
Currently, we're considering the following software development tools and
A. "Compiler Construction Guide" (per chip) - chip implementation details
(dispatch characteristics, functional unit capabilities, pipeline stage
descriptions, instruction cycle timings, etc.), descriptions of
scheduling methods, example scheduling scenarios, etc.
B. "System Guide" (per OS) - calling / linkage conventions, application
binary layout, object module formats, debug information, etc.
C. "Architecture Reference" - contents of PowerPC Architecture Books
I through III on CD ROM in hypertext format.
D. Architectural Simulator - software simulation of the chip (based on
the PowerPC Visual Simulator), complete with debugger-style GUI, ability
to load binaries in a popular object module format, produce human readable
traces, extensive breakpoint facilities, instruction undo, etc.
E. Cycle Timer - takes traces generated by the architectural simulator and
provides cycle-resolution pipeline traces, flags stalls, provides
execution statistics (instructions-per-cycle, MIPS, etc.), cache
F. Reference Compiler - sample functional compiler back-end provided as
source to demonstrate optimization technologies or to incorporate in
your own compiler (royalty free). Design and intermediate language
specs provided as well.
G. Cross Assembler and Linker
H. Symbolic Debugger - also provides register-level access, C/C++
compatibility, remote-target debug (via serial link, for instance)
I. Low-Level Debugger - attaches via umbilical connection from host to
JTAG port on target CPU (little or no support system services needed
Here's your chance! IBM is all ears, tell us what you want. What's missing
in the above list? What should we discard? What capabilities should we
consider? What platforms should the tools run on? ... You get the idea.
Send your responses to my e-mail: firstname.lastname@example.org.
Many thanks in advance,
PowerPC Development Tools Architecture
IBM Microelectronics Division
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