|Looking for Fine Grained Parallel Compiler Refs firstname.lastname@example.org (1994-04-21)|
|Re: Looking for Fine Grained Parallel Compiler Refs email@example.com (1994-04-30)|
|From:||firstname.lastname@example.org (Michael A. Hopper)|
|Organization:||Electrical and Computer Engineering, Georgia Tech.|
|Date:||Thu, 21 Apr 1994 17:14:55 GMT|
I am looking for papers on parallelizing compilers for fine grain message
passing computer architectures. I am interested in the exploitation of
fine/medium grained parallelism (this may be called task level
parallelism, it is just above instruction level parallelism). I am
looking specifically for compiler techniques to recognize this parallelism
and map the code and data to the processors. The target architecture is a
message passing MIMD with very fast I/O and limited memory per processor.
It shares some similarities with the MIT J-Machine.
Does anyone have references on the current work in this area? Thanks for
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