|200 way issue? firstname.lastname@example.org (1993-09-29)|
|Re: 200 way issue? email@example.com (1993-09-30)|
|Re: 200 way issue? firstname.lastname@example.org (1993-09-30)|
|Re: 200 way issue? grover@brahmand.Eng.Sun.COM (1993-09-30)|
|Re: 200 way issue? email@example.com (1993-09-30)|
|Re: 200 way issue? firstname.lastname@example.org (1993-10-01)|
|Re: 200 way issue? email@example.com (1993-10-01)|
|Re: 200 way issue? firstname.lastname@example.org (Dave Gillespie) (1993-10-04)|
|From:||email@example.com (Anton Ertl)|
|Organization:||Institut fuer Computersprachen, Technische Universitaet Wien|
|Date:||Thu, 30 Sep 1993 11:11:29 GMT|
firstname.lastname@example.org (David Moore) writes:
> HOWEVER, the question I want to raise is this: How many way issue can one
> actually use on real code.
> Suppose, for example, we took the spec benchmarks and optimized for an
> infinite issue machine. Now suppose we built a histogram of actual number
> of instructions issued per machine cycle. Has anyone published a paper on
> what this histogram would look like?
There have been lots of papers on the limits of instruction-level
parallelism, and I also remember one that tried to do something like what
you are asking for (I don't have the reference handy, but the paper was
not so impressive anyway).
To answer your first question: It's not hard to make use of all issue
bandwidth available, due to one technique: speculative execution. Just
execute all instructions on any possible execution path, where the data is
ready. With infinite loop unrolling and combining (a transformation) a
loop like SAXPY would even use an infinite issue machine 100%. Although of
course only 0% of that work would be really useful. (Note that there are
also some problems with exceptions of speculatively executed instructions,
but with a bit of architectural support they can be solved.)
The big question is: With the limited issue bandwidth we have, which
instructions do we execute speculatively in order to maximize the amount
of really useful work done. There have been lots of papers about this
question, just search in your literature database for suftware pipelining
and (global) scheduling or take a look in the MICRO proceedings.
M. Anton Ertl, email@example.com
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