Scheduling for RISCs: more on List-scheduling

Mayan Moudgill <moudgill@cs.cornell.EDU>
Wed, 19 May 1993 05:07:28 GMT

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Related articles
List-scheduling: a RISC-driven solution? moudgill@cs.cornell.EDU (Mayan Moudgill) (1993-05-11)
Scheduling for RISCs: more on List-scheduling moudgill@cs.cornell.EDU (Mayan Moudgill) (1993-05-19)
Re: List scheduling and register allocation (1993-05-22)
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Newsgroups: comp.compilers
From: Mayan Moudgill <moudgill@cs.cornell.EDU>
Keywords: optimize
Organization: Cornell Univ. CS Dept, Ithaca NY 14853
References: 93-05-051
Date: Wed, 19 May 1993 05:07:28 GMT

I asked earlier whether anyone had seen any work on NON-list-scheduling
algorithms in the period 79-92. I haven't heard any examples for that
period for RISC architectures. So:
(This is all in the context of basic block scheduling on a RISC)

In RISC scheduling, schedules tend to be closely packed. (I wonder---does
anyone have a paper comparing length of schedule against number of
operations being scheduled?) This assumes that most operations have a use
latency of 1, and most of the rest have a use latency <= 4, and that the
units have issue latencies of 1.

In a RISC, any spill will (probably) extend the schedule length. A
schedule is fairly tightly packed, and each store and load inserted in the
schedule is going to bump into other instructions being issued at the same
time, forcing them later.

In such a case, the best approach to basic-block scheduling is to optimize
for register pressure, minimizing spills, and then schedule operations so
that every issue cycle contains at least one operation.

If that is the case, then a pre-pass register allocator with a
list-scheduler would produce perfectly adequate schedules.

Any comments?


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