Related articles |
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How many vector registers are useful? kirchner@uklira.informatik.uni-kl.de (1993-01-25) |
Re How many vector registers are useful? ssimmons@convex.com (1993-01-26) |
Re: Re How many vector registers are useful? billms@corp.corp.mot.com (1993-01-28) |
Re: Re How many vector registers are useful? idacrd!desj@uunet.UU.NET (1993-01-31) |
Re: Re How many vector registers are useful? billms@corp.mot.com (1993-02-02) |
Newsgroups: | comp.compilers |
From: | billms@corp.corp.mot.com (Bill Mangione-Smith) |
Keywords: | architecture, vector |
Organization: | University of Michigan |
References: | 93-01-174 93-01-191 |
Date: | Thu, 28 Jan 1993 14:52:45 GMT |
ssimmons@convex.com (Steve Simmons) writes:
No, I do not know of any published studies that state the optimal number
of vector registers. However, there are costs as more vector operators
are added. These costs are expansion of instruction format, more complex
micro code within the vector unit, more complex chaining analysis in both
the compilers and vector unit, etc... Ultimately, this cost is paid for by
the custumer.
Santosh Abraham, Ed Davidson, and I had a paper two asplos's ago that
looked at the minimal number of vector registers required for specific
codes. The question of the optimal is really tough to address for all the
obvious reasons: the dependence on compiler technology, variability in
program demands, and the real hardware costs of various machine designs
(like the register-fu interconnect). Because of this we decided to focus
on the minimal number of registers required to achieve optimal
performance. Sure, in theory its an intractable problem for a compiler,
but my experience along the way suggests that in fact you can often find
these optimal performance schedules without killing yourself, and the
early discoveries are often fairly close to the minimal (in terms of
register demands).
Last summer we had a follow up paper at ICS that presented a theory for
why the asplos results looked they way they did. This paper extended the
work on register demands to vliw and single issue machines, though still
focused on vectorizable loop codes.
Bill
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