|Optimizations for Pipelined Processors firstname.lastname@example.org (1993-01-21)|
|Re: Optimizations for Pipelined Processors email@example.com (1993-01-22)|
|Re: Optimizations for Pipelined Processors firstname.lastname@example.org (1993-01-22)|
|Re: Optimizations for Pipelined Processors email@example.com (1993-01-22)|
|From:||firstname.lastname@example.org (Alon Ziv)|
|Date:||Thu, 21 Jan 1993 11:13:46 GMT|
|Keywords:||optimize, parallel, question, comment|
During a discussion with a friend who works for Intel in microprocessor
developement, we found out that nothing is ever taught about implementing
compiler back-ends for pipelined processors; in fact, it would even seem
that some common optimizations would be potentially harmful on such a uP,
while others---such as loop unrolling---have unexpected benefits.
Moreover, there are some ``weird'' schemes used by assembly programmers on
such processors (such as `mixing' instruction sequences for long,
essentially independent computations) which are far out from standard
practice in optimization.
So, the question is: _is_ there any research going on for these ideas? I
would assume that it has started, and---if so---would very much like to
have some references about progress so far, as it seems to be
(potentially, at least) VERY interesting.
Internet: email@example.com . __
[There's been plenty of work on pipeline scheduling. I'm sure readers will
send in citations. -John]
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