|Re: Are 64 Int or FP registers useful? firstname.lastname@example.org (1992-09-14)|
|Re: Are 64 Int or FP registers useful? email@example.com (1992-09-16)|
|Re: Are 64 Int or FP registers useful? firstname.lastname@example.org (1992-09-17)|
|Re: Are 64 Int or FP registers useful? email@example.com (Dave Gillespie) (1992-09-17)|
|Re: Are 64 Int or FP registers useful? firstname.lastname@example.org (1992-09-17)|
|Re: Are 64 Int or FP registers useful? email@example.com (1992-09-19)|
|From:||Dave Gillespie <firstname.lastname@example.org>|
|Date:||Thu, 17 Sep 1992 19:03:12 GMT|
The Intel 860 CPU tends to require lots of FP registers. It's not hard to
use up all 32 registers in a heavily pipelined loop. (Our most
complicated loop, used in a back-propagation algorithm, just barely
manages to fit in exactly 32 regs.)
In our case, the loop in question is unrolled by a factor of 12 in order
to get maximum performance. (Which, incidentally, is 100% utilization of
both the adder and the multiplier units; there's a reason the 860 is as
crufty as it is...) The register usage comes from needing to work on so
many iterations of the loop at once.
On the other hand, I've never seen a compiler that could really take
advantage of the 860's pipelining; our inner loops are all hand-coded.
860 optimizers tend to be essentially vectorizing compilers, where the
"vector instructions" are hand-coded assembly language routines.
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