|Caller allocates space for callee-save registers email@example.com (1992-05-21)|
|Register + Offset vs. Register Indirect firstname.lastname@example.org (1992-06-07)|
|Re: Register + Offset vs. Register Indirect igor!davidm@uunet.UU.NET (1992-06-08)|
|Re: Register + Offset vs. Register Indirect email@example.com (Dave Berry) (1992-06-09)|
|From:||Dave Berry <firstname.lastname@example.org>|
|Keywords:||architecture, registers, optimize, storage|
|Organization:||Laboratory for the Foundations of Computer Science, Edinburgh U|
|Date:||Tue, 9 Jun 1992 14:12:08 GMT|
igor!davidm@uunet.UU.NET (David Moore) writes:
>The chief advantage of register+short immediate addressing is to avoid
>having to increment large numbers of induction variables in loops.
I think it's also useful in implementing runtimes that use tagged garbage
collectors. A common scheme is to use the low bit of a word to encode its
status. If the bit is 0, then the word is a 31-bit integer. If the bit
is 1, then the word is a pointer. Any memory access adds 3 to the word to
get an address on a word boundary.
I suppose that if register+short immediate addressing wasn't available
then you could dedicate a register to hold the 3 offset, provided that the
addition of this offset wasn't any slower. (I don't know enough about
specific chips to comment on this.)
[Some architectures scale the offset by the size of the datum, which often
makes Lisp implementors unhappy. -John]
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