Compiler Back End short course (Michael Wolfe)
5 Feb 92 20:57:54 GMT

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Newsgroups: comp.compilers
From: (Michael Wolfe)
Keywords: courses, optimize
Organization: Oregon Graduate Institute, Beaverton, OR
Date: 5 Feb 92 20:57:54 GMT

This summer, the Oregon Graduate Institute is offering a new

    Summer Intensive Tutorial on
High Performance Compiler Back Ends
            June 22-24, 1992
            Portland, Oregon

The full details of this course are available electronically
via anonymous ftp at [] as pub/tiny/HPBE.

Or send email to (for technical inquiries) (for registration and other information)

What follows is the (lengthy) course outline and schedule.
See also the companion posting with the outline for our highly successful
High Performance Compilers short course.



1. Pipelined Processor Architecture (3 hours)
    - RISC instruction set
    - pipelined functional units
    - large register file
    - datapaths
    - vector instruction set
    - cache memory
. Control Unit Options
    - register windows
    - VLIW instruction set
    - super-scalar control unit
    - register renaming
    - multithreading
. Representative Architectures
    - Multiflow Trace/300
    - Cydrome Cydra 5
    - IBM RS/6000
    - Intel i860

2. Compiler Framework (.5 hour)
. Where the back end sits
    - front end
    - high level optimizations
    - back-end optimizations
    - code generation
. Data structures to support optimization
    - control flow graph, basic blocks
. Analysis methods
    - live variables
    - reaching definitions
    - use-def chains

3. Classical Code Generation (2 hours)
    - hand written code generators
    - table drive code generators
    - tree walk

4. Strength Reduction (2 hours)
    - induction variables


5. Register Assignment (3 hours)
    - register coloring
    - spilling heuristics

6. Instruction Scheduling (4 hours)
    - filling delay slots
    - "Trace Scheduling" (tm)
    - extended basic block formation


7. Instruction Scheduling in Loops (5 hours)
    - software pipelining
    - polycyclic scheduling
    - loop unrolling
    - loop peeling
    - register assignment in loop

  8. Optimizations for Extra Parallelism (3 hours)
    - inline function expansion
    - speculative execution
    - conditional execution
    - prefetching



Lectures: Monday-Wednesday, 8:00am-5:00pm

Lunches: Monday-Wednesday, noon-1:00pm

Breaks: 10:00-10:15am, 3:00-3:15pm

Reception: Monday, 7:00-10:00pm, at the The Lakes

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