|MIPS R2000 interpretor email@example.com (1991-09-28)|
|Re: MIPS R2000 interpretor firstname.lastname@example.org (1991-10-01)|
|Re: MIPS R2000 interpretor email@example.com (1991-10-09)|
|From:||firstname.lastname@example.org (Vadim Antonov)|
|Organization:||DEMOS, Moscow, USSR|
|Date:||Wed, 9 Oct 91 17:45:26 GMT|
I'm currently writing one including CP0 and cache simulation -- if someone
needs it I could send the (undebugged) sources. I do not plan to make it a
complete product, I simply need a simulator of a simple multiprocessor
machine for my research project and too lazy to invent my own device :-)
BTW, I have no live MIPS processor (and all books lack details) and want
to ask some trivia questions:
1. How LWL and LWR do really work on *aligned* words?
2. What BCT0 and BCF0 really do?
3. Is there any functionality of CP0 *control* registers?
4. A book says that raising TLB Shutdown condition will disable TLB
and address translation will produce *undefined* results. Is there
any regular way to catch this situation from software?
5. I'd like to simulate a simple disk subsystem and tty and want to
make it similar to some existant hardware. Any suggestions?
6. How to implement inter-processor signalling and locks on MIPS-based
Excuse for abusing your attention :-) I do not expect there is a lot of
people interested in these details thus please answer by e-mail.
DEMOS, Moscow, USSR
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