|VHDL Experience firstname.lastname@example.org (1991-07-22)|
|Re: VHDL Experience email@example.com (Peter Ludemann) (1991-07-26)|
|From:||firstname.lastname@example.org (Arthur Castonguay)|
|Date:||Mon, 22 Jul 91 10:17:51 EDT|
I'm embarking on the adventure of writing a VHDL compiler. Its going
to be in a silicon compiler and will accept VHDL source and output
a data flow graph which is then spun, tangled, and mutilated to produce
the final output. I'm currently doing the lexical analysis work. Any
experiences or warnings about this type of work and VHDL in particular
would be greatly appreciated before I learn them myself. I'm using
flex and bison. I've heard that VHDL doesn't lend itself nicely to these
tools. If so, could someone explain why?
Thanks for any input,
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