|Comprehensive i860 performance report firstname.lastname@example.org.Virginia.EDU (1991-05-15)|
|Re: Comprehensive i860 performance report email@example.com.Virginia.EDU (1991-05-15)|
|From:||firstname.lastname@example.org.Virginia.EDU (Steven A. Moyer)|
|Keywords:||i860, performance, report|
|Organization:||Dept. of Computer Science, University of Virginia|
|Date:||Mon May 20 23:00:21 1991 GMT|
A number of people in various newsgroups have requested information concerning
the performance of the i860 and/or i860 compilers. A study just completed
at the University of Virginia examines in depth the processor-memory
interrelationship for a board consisting of an i860 and memory subsystem
constructed from page-mode DRAMs.
>From an understanding of this interrelationship, guidelines are established
for implementing inner-loop operations in a manner consistent with the
processor architecture and memory system performance characteristics; by
adhering to these guidelines the assembly language programmer or compiler
writer can realize a 200-300% increase in performance over code generated
in a "straight-forward" fashion.
The implementation techniques presented throughout the report are dependent
on a memory system constructed with static-column or page-mode DRAMs. In
addition, the report focuses on vector operations (BLAS-like routines) and
scientific computations built on top of them.
To receive a copy of this report, send a request to:
Institute for Parallel Computation
School of Engineering and Applied Science
University of Virginia
Charlottesville, VA 22903
ask for IPC-TR-91-007 "Performance of the iPSC/860 Node Architecture"
Steve Moyer, University of Virginia, E-mail: email@example.com
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