|Re: Instruction reordering (scheduling) for SPARC firstname.lastname@example.org (1991-03-12)|
|Re: Instruction reordering (scheduling) for SPARC email@example.com (1991-03-13)|
|From:||firstname.lastname@example.org (Eliot Moss)|
|Organization:||Dept of Comp and Info Sci, Univ of Mass (Amherst)|
|Date:||13 Mar 91 13:45:53 GMT|
In article <9103122023.AA14689@lpi.liant.com> email@example.com (Rick Gorton) writes:
[re optimizing code for a Sparc's pipeline]
The better news is that, yes, these 3 chipsets all happen to have the same
cycle times. But you cannot guarantee this to be true in the future. It
will be messy to write an instruction scheduler for a compiler which can
generate differently scheduled code for different chipsets by merely using a
different compile-time switch.
Actually, this may not be true of the new improved gcc (v 2.0) with its
instruction scheduling. Since it is driven by essentially tabular
information, it *might* be possible to switch tables based on a switch.
Michael Tiemann could probably say how hard it would be. It would certainly
be easy to generate different versions of the compiler without changes only
to the machine description information used for instruction scheduling.
J. Eliot B. Moss, Assistant Professor
Department of Computer and Information Science
Lederle Graduate Research Center
University of Massachusetts
Amherst, MA 01003
(413) 545-4206, 545-1249 (fax); Moss@cs.umass.edu
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