Need info on SPARC memory behavior

vanroy@pisces.Berkeley.EDU (Peter Van Roy)
Thu, 7 Mar 91 14:24:19 PST

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Need info on SPARC memory behavior vanroy@pisces.Berkeley.EDU (1991-03-07)
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Newsgroups: comp.compilers,comp.arch
From: vanroy@pisces.Berkeley.EDU (Peter Van Roy)
Keywords: SPARC, question
Organization: Compilers Central
Date: Thu, 7 Mar 91 14:24:19 PST

I am in the process of retargeting a compiler for the SPARC. I am building
an instruction reordering stage. To achieve the best performance, I need
information about the memory system and the pipeline structure of several
implementations of the SPARC.

The machines I am interested in are the SPARCstation 1+ and the SPARCstation 2.

Does the machine have a cache? If so, what are its characteristics?

What operations will insert a bubble, i.e. a no-op cycle, in the pipe?
For example:
How many cycles are needed to do a load and a store?
Is there any advantage (apart from needing only a single instruction
fetch) to the double-word loads and stores?
Does using a register the cycle after it is loaded create a bubble?
Does doing two loads or stores in sequence create a bubble?

Thanks very much,

Peter Van Roy
Computer Science Division
University of California, Berkeley

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