|Machine Descriptions Chuck_Lins.SIAC_QMAIL@gateway.qm.apple.com (Chuck Lins) (1991-02-20)|
|Re: Machine Descriptions email@example.com (1991-02-22)|
|From:||firstname.lastname@example.org (David Bradlee)|
|Summary:||retargetable instruction scheduling|
|Keywords:||GCC, design, optimize|
|Organization:||U of Washington, Computer Science, Seattle|
|Date:||22 Feb 91 01:16:35 GMT|
In article <9102201924.AA14610@internal.apple.com>, Chuck_Lins.SIAC_QMAIL@gateway.qm.apple.com (Chuck Lins) writes:
> It seems from all the papers I've read on this topic that the research has
> focused on the VAX-11, MC680x0, PDP-11, IBM 360/370 kind of architecture. I
> don't remember much being done with SPARC, MIPS, HP-PA RISC, 88000, ARM,
Yes, most previous work was on CISCs. But recently, Robert Henry,
Susan Eggers and I have worked on retargetable instruction scheduling
for RISCs. We build back ends that include instruction selection,
register allocation and instruction scheduling from a machine
description. The description is more like the Fraser/Davidson model
than the Graham/Glanville. A paper on the system will appear in this
year's SIGPLAN'91 PLDI conference (June). David Bernstein and Michael
Rodeh will also have a paper there that talks about their system for
scheduling across basic block boundaries.
> It seems that we're a very long way from a truely general machine
> description mechanism.
Nothing is truly general. Our description can cover a lot of RISCs
but some features are hard. It's a start. I think we'll see a lot
more on instruction scheduling in the next few years.
Department of Computer Science and Engineering, FR-35
University of Washington
Seattle, WA 98195
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