|Announcement: Workshop on Code Generation email@example.com (1991-02-08)|
|From:||firstname.lastname@example.org (Robert Giegerich)|
|Keywords:||CFP, conference, code, parallel, optimize|
|Date:||Fri, 08 Feb 91 16:10:29 GMT|
Workshop on Code Generation
International Conference and Research Center for Computer Science
Schloss Dagstuhl, May 20-24, 1991
Current issues in code generation
Current tools for code generation are built around code selection based on
pattern matching. We now have a good understanding and efficient
implementations for pattern matching. It is still a problem of current
research how to integrate other subtasks of code generation with the pattern
based approach in a satisfactory way.
Meanwhile, RISC architectures tend to make code selection (by itself)
trivial, while creating new tasks of effectively using pipelined CPUs.
Instruction scheduling and delayed branch optimization are problems
reoccuring with each new RISC processor, for which generally accepted models
are not available.
Another source of CPU parallelism is the presence of multiple functional
units. VLIW-architectures require non-local code rearrangements, and
introduce new complexity by the interaction between scheduling and global and
local register allocation.
In the implementation of non-imperative languages, abstract machines are used
for code generation. Although these machines are different for logical,
functional or object-oriented machines, many problems reoccur, like register
allocation or pattern matching. While some of these abstract machines are
being implemented in hardware, in most cases, concrete code for conventional
machines must be produced from the abstract machine code.
Generally, the sensitivity to the question of reliable systems is increasing.
In hardware synthesis as well as in compiler construction, first attempts
have been made to use automated proof systems for verification. The idea of a
fully verified hard- and software system is still a challenging goal.
What is the impact of code generation work on compiler and hardware design?
Techniques used in code generation may prove useful also in other compilation
phases. Retargettability can only be achieved based on an appropriate,
modular compiler structure. Last not least, research on code generation
should support hardware design by a classification of cpu properties that
make effective cpu utilization feasible at a reasonable price.
Goals of the Workshop on code generation
While new problems and solutions have evolved in recent years, the work in
the areas outlined above has proceeded in a rather isolated way. Recent
conferences have not provided a forum to bring together a significant number
of researchers in the field. This workshop is intended to provide such a
forum for the exchange of results and ideas. Sufficient time will be
allocated for in-depth presentation and detailed discussion, both in large
and in small groups. The outcome of the workshop should be an in-depth
documentation of the state of the field, and an outline of the major themes
of research for the next years.
The workshop is sponsored by IFBI Schloss Dagstuhl, a new international
conference and research center for computer science. The site of the IFBI
institute and site of the workshop is a beautiful castle in the forests of a
low mountain range in the Saarland (Germany). A computer science library as
well as a local network of high performance workstations are available at the
institute. The workshop is limited to ca. 40 participants and is by
invitation only. The institute provides full board and lodging at a nominal
fee, and supports, if needed, the participants' travel within Germany. For
participants from USA, the organizers will attempt to obtain a block travel
grant from NSF.
Currently, the workshop is planned to include sessions on
- Formal Methods
- Code Generation for Nonimperative Languages
- Register Allocation
- Parallel Architectures.
All kinds of contributions are solicited - survey papers that
reflect the state of the art, reports on completed projects,
and, in particular, long or short presentations of ongoing
However, submission of a paper is not mandatory.
For the workshop, preliminary versions of papers are required. Final versions
of selected contributions will be published in a proceedings volume, to
appear in Springer LNCS.
Researchers who think they could contribute to and benefit from the workshop
should send e-mail to both the coordinators. Please indicate your major field
of interest, and the topic of an eventual contribution.
Dates and Deadlines
Susan L. Graham Robert Giegerich
EE/CS Division Universitaet Bielefeld
University of California Technische Fakultaet
511 Evans Hill P.O.Box 86 40
Berkeley, CA 94720 4800 Bielefeld 1
Workshop date: May 20-24th, 1991
Location: International Conference and Research Center
for Computer Science,
Schloss Dagstuhl, Germany (near Saarbruecken;
easily reachable from Frankfurt Airport)
Workshop fee: DM 150,- (ca. US$ 100,-; includes room and
Apply for invitation: before Feb. 28th, 1991
Preliminary papers due: April 1st, 1991
Accomodation for accompanying persons may be arranged in the
surrounding communities. Note that the overall ambience is very
Robert Giegerich * University of Bielefeld * D-4800 Bielefeld 1 * W-GERMANY
Email: email@example.com * Tel.: +49 521 106 2908
Horst Hogenkamp * University of Bielefeld * D-4800 Bielefeld 1 * W-GERMANY
Email: firstname.lastname@example.org * Tel.: +49 521 106 2908
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