Re: Register Allocation

dds@cc.ic.ac.uk (Diomidis Spinellis)
Tue, 27 Feb 90 13:02:55 GMT

          From comp.compilers

Related articles
[24 earlier articles]
register allocation dgb@cs.washington.edu (1989-11-22)
Re: register allocation larus@primost.wisc.EDU (1989-11-24)
Register Allocation napi@rangkom.MY (1990-02-17)
Re: Register Allocation cik@l.cc.purdue.edu (1990-02-15)
Re: Register Allocation wendyt@cs.washington.edu (1990-02-26)
Re: Register Allocation Moss@cs.umass.edu (1990-02-25)
Re: Register Allocation dds@cc.ic.ac.uk (1990-02-27)
Register Allocation nandu@jupiter.cs.clemson.edu (1993-03-31)
Register Allocation rajiv@polya.ece.wisc.edu (1993-08-31)
Re: Register Allocation preston@dawn.cs.rice.edu (1993-09-06)
Register Allocation ashish@usl.edu (Ashish Ashtekar) (1996-04-02)
| List of all articles for this month |

Date: Tue, 27 Feb 90 13:02:55 GMT
Newsgroups: comp.compilers
References: <1990Feb20.155619.3121@esegue.segue.boston.ma.us> <1990Feb24.210757.4202@esegue.segue.boston.ma.us>
From: dds@cc.ic.ac.uk (Diomidis Spinellis)
Organization: Imperial College Department of Computing
Keywords: Pointers

In article <1990Feb24.210757.4202@esegue.segue.boston.ma.us> cik@l.cc.purdue.edu (Herman Rubin) writes:
>In article <1990Feb20.155619.3121@esegue.segue.boston.ma.us>, napi@rangkom.MY (Mohd Hanafiah b. Abdullah) writes:
>> How does one perform register allocation on scalar variables that may
>> be pointed to by others?
[...]
>and I have no difficulty using machine language. The only mainframes whose
>instruction set I have known which are appropriately set up in hardware for
>this are the long obsolete UNIVAC 1108 and 1110.
[...]
>[The PDP-10/DEC-20 has addressable registers as well, but as pointed out
>elsewhere that's only a small part of the problem. As soon as you call
>another routine, it's liable to save the register and put something else
>there, and you lose. -John]


Addressing registers is possible in the Texas Instruments TM 990 series
of minis and TMS-9900, TMS-9950 microprocessors. All 16 general
purpose registers are in a memory block pointed by a single processor
register the workspace pointer. With some care one can implement
register windowing. Saving the registers is then just a change of the
workspace pointer; pointers that point to registers in previous stack
frames still point to the correct object. On the 9995 the registers can
be located on on-chip RAM, so the performance is not affected by the cost
of external memory accesses.


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