|Compiler optimization and RISC. email@example.com (1989-11-03)|
|Re: Compiler optimization and RISC. firstname.lastname@example.org (1989-11-07)|
|Re: Compiler optimization and RISC. email@example.com (1989-11-15)|
|From:||firstname.lastname@example.org (Peter C. Damron)|
|Keywords:||List of references.|
|Date:||7 Nov 89 21:43:23 GMT|
|Organization:||University of Washington, Computer Science, Seattle|
In article <1989Nov3.email@example.com> firstname.lastname@example.org (Sanjeev Kumar) writes:
>I am looking for any pointers to literature on compiler optimization
>for RISC processors. More specifically, the effect of RISC technology
>on code generation.
There are not any articles specifically on the effect of RISCs on compilers
that I can think of, but you can look at the trends in compiler research
to find what effects are important. Also you can look at what the
architectural differences are to see what compilers have to worry about.
The back-end of a compiler typically includes 4 phases: optimization,
instruction selection, register allocation, and instruction scheduling.
Optimization is about the same for both RISC and CISC.
For the old style CISC processors, instruction selection was the key
problem area, especially when combined with register allocation.
Making effective use of addressing modes was a problem that has been
solved with the current generation of tree pattern matching code generators.
Compilers for CISC do not usually worry about instruction scheduling.
For RISC processors, instruction selection is not much of an issue,
since there are few choices. However, the processor pipeline is typically
more exposed, so instruction scheduling is much more important.
RISC processors also include more registers, which makes register allocation
more important, especially more global register allocation.
Original thoughts may have been that compilers for RISC would be simpler
than those for CISC, but it seems only that one difficult problem
(instruction selection) has been traded for another difficult problem
Take a look at articles on register allocation and instruction scheduling
in any of the recent compiler conferences, published annually in June
in ACM Sigplan Notices (well almost, 1979, 1982, 1984, 1986, 1988, 1989).
Hope this helps,
Peter C. Damron
Dept. of Computer Science, FR-35
University of Washington
Seattle, WA 98195
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