|Compiler optimization and RISC. firstname.lastname@example.org (1989-11-03)|
|Re: Compiler optimization and RISC. email@example.com (1989-11-07)|
|Re: Compiler optimization and RISC. firstname.lastname@example.org (1989-11-15)|
|From:||email@example.com (Sanjeev Kumar)|
|Keywords:||List of references.|
|Date:||3 Nov 89 10:08:06 GMT|
|Organization:||Rutgers Univ., New Brunswick, N.J.|
I am looking for any pointers to literature on compiler optimization
for RISC processors. More specifically, the effect of RISC technology
on code generation.
I have already looked at tutorial/text-book level literature on RISC,
and pointers to any papers in conf./journals would be welcome.
Sanjeev Kumar. ( firstname.lastname@example.org )
Phone: Off: (201)932-3766. Home: (201)878-2940.
Dept. of Computer Science, RUTGERS, New Brunswick, NJ08903.
[The IBM 801 project did a great deal of compiler work. See SIGPLAN 17:6
pp. 22-31, 98-105, and 114-118. Also see US Patents 4,571,678, 4,656,582,
4,656,583, 4,642,764, and 4,642,765. The Stanford MIPS project expected
the compiler or assembler to schedule memory accesses; there must be some
papers there that readers can point to. -John]
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