|Compilers for Decoupled Architectures. email@example.com (Theodore Stevens Norvell) (1988-12-15)|
|Re: Compilers for Decoupled Architectures. firstname.lastname@example.org (1988-12-20)|
|From:||email@example.com (Sean Fagan)|
|Date:||20 Dec 88 18:19:56 GMT|
|Organization:||The Santa Cruz Operation, Inc.|
In article <firstname.lastname@example.org> Theodore Stevens Norvell <email@example.com> writes:
>I am interested in references on compilers for decoupled architectures and
>machines with a similar register structure (such as the CDC 170 and the Crays).
[my favorite word 8-)]
[brief description of splitting of registers given]
Well, I worked on a Cyber 170 for quite a while, and looked a bit into what
GCC would need to get it to work (you've always wanted 60-bit char's right?).
Basicly, there isn't a big problem for compiler written for that machine.
FTN5, for the Cyber, would put index registers and DO loop variables into the
18-bit B registers (unless you told it you wanted "big" DO loops, in which
case it used a 60-bit X register). Making gcc work, on the other hand, would
not do such a thing (because a B register is a register of class Pointer, for
which it has at least some basic hooks), unless the person describing the
cyber to gcc were really clever (which I'm not 8-)).
Also, in your example, if N is a constant, and less than 2**17, than it would
be best to put it into an index register. A[i], B[i], and z should go into
data registers, as you said. However, on a Cray, you could probably vectorize
it, splitting it up (at run time?) to do it in chunks of 64 A's and B's.
Sean Eric Fagan | "Merry Christmas, drive carefully and have some great sex."
seanf@sco.UUCP | -- Art Hoppe
(408) 458-1422 | Any opinions expressed are my own, not my employers'.
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