Re: Fat references

George Neuner <>
Thu, 07 Jan 2010 01:57:45 -0500

          From comp.compilers

Related articles
[28 earlier articles]
Re: Fat references (Kaz Kylheku) (2010-01-05)
Re: Fat references (BGB / cr88192) (2010-01-05)
Re: Fat references (Jon Harrop) (2010-01-06)
Re: Fat references (Jon Harrop) (2010-01-06)
Re: Fat references (George Neuner) (2010-01-07)
Re: Fat references (George Neuner) (2010-01-07)
Re: Fat references (George Neuner) (2010-01-07)
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From: George Neuner <>
Newsgroups: comp.compilers
Date: Thu, 07 Jan 2010 01:57:45 -0500
Organization: A noiseless patient Spider
References: 09-12-045 09-12-055 10-01-005
Keywords: storage, GC, architecture
Posted-Date: 08 Jan 2010 10:23:59 EST

On Fri, 01 Jan 2010 06:10:02 +0000, Jon Harrop <>

>Kaz Kylheku wrote:
>> On 2009-12-29, Jon Harrop <> wrote:
>>> I couldn't be bothered to allocate a separate header so,
>>> instead, I pulled the GC metadata into the reference. So my references
>>> are now "fat": a quadword of pointer to run-time type, array length or
>>> union type tag, pointer to mark state and pointer to the actual data
>>> itself.
>> So now you have references that can't fit into a machine register.
>If you don't have 128- or 256-bit registers on your 32- or 64-bit machine,

Comparing your fat references using large SIMD registers is relatively
easy (but still 2 instructions on most architectures - not as simple
as comparing a single value). But the SIMD registers on most (all?)
CPUs can't dereference pointers ... which means you still have to get
the pointer bits into a general register to use it. Any data on how
much of a hit you take by reloading or extracting pointers for use
after the tag check?

Or are you just pointing out that some CPUs have large(r) registers?

Two issues you might consider are: 1) few current machines have memory
buses larger than 64-bits even if they have larger registers; and 2)
for multiple cores or processors you need to consider the bus
arbitration scheme ... if the bus is arbitrated cycle-by-cycle there
is no guarantee that a large SIMD register load/store will be atomic.


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