|[15 earlier articles]|
|Re: Guidelines for instruction set design? email@example.com (2009-05-12)|
|Re: Guidelines for instruction set design? firstname.lastname@example.org (George Neuner) (2009-05-12)|
|Re: Guidelines for instruction set design? email@example.com (Walter Banks) (2009-05-13)|
|Re: Guidelines for instruction set design? DrDiettrich1@aol.com (Hans-Peter Diettrich) (2009-05-13)|
|Re: Guidelines for instruction set design? cfc@shell01.TheWorld.com (Chris F Clark) (2009-05-18)|
|Guidelines for instruction set design? firstname.lastname@example.org (Richard O'Keefe) (2009-05-26)|
|Re: Guidelines for instruction set design? email@example.com (2009-06-03)|
|Date:||Wed, 3 Jun 2009 00:37:21 -0700 (PDT)|
|Posted-Date:||03 Jun 2009 05:50:59 EDT|
Most C compilers expect a basic set of instructions to be supported by
a processor. A good way to check is to map the standard "operators x
type precedence" table from K&R to the processor's instruction set.
This helps quickly discover missing instructions.
Next would be the "addressing modes". Most custom (and generally DSP)
processors tend to support complex addressing modes.
A good guideline is to make sure there are standard addressing modes
supported like register direct, register indirect (base) and register
indirect with offset (base+offset). If a base + index addressing mode
is supported, just make sure any index register can be used with any
base address (if that can be done without sacrificing too much on the
Of course, the processor must have a basic set of control flow
instructions (ability to call/return/jump) and a good addressing mode
for argument passing and access. Modern processors normally include an
addressing mode that enables the compiler to avoid push/pop's
completely by setting up a full-frame for a function (including stack
space for outgoing arguments) upfront and accessing the arguments
directly using an offset from the stack pointer (gcc includes support
In general a compiler-friendly processor must minimize dependencies
between orthogonal features. A good porting specification document
that maps C-level features to the processor in terms of ABI (calling
conventions, type mapping, register usage) and operations will greatly
help in effective communication between all the stake holders. It is
"normal" in the early history of a new processor architecture for the
processor designers to incorporate at least a few changes based on the
feedback from the compiler architect.
Hope that helps.
Gopi Kumar Bulusu
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