Re: Guidelines for instruction set design?

toby <toby@telegraphics.com.au>
Sun, 10 May 2009 23:01:28 -0700 (PDT)

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Re: Guidelines for instruction set design? bartc@freeuk.com (BartC) (2009-05-05)
Re: Guidelines for instruction set design? gneuner2@comcast.net (George Neuner) (2009-05-05)
Re: Guidelines for instruction set design? walter@bytecraft.com (Walter Banks) (2009-05-06)
Re: Guidelines for instruction set design? gmt@cs.arizona.edu (2009-05-06)
Re: Guidelines for instruction set design? dot@dotat.at (Tony Finch) (2009-05-07)
Re: Guidelines for instruction set design? gneuner2@comcast.net (George Neuner) (2009-05-10)
Re: Guidelines for instruction set design? toby@telegraphics.com.au (toby) (2009-05-10)
Re: Guidelines for instruction set design? anton@mips.complang.tuwien.ac.at (2009-05-12)
Re: Guidelines for instruction set design? gneuner2@comcast.net (George Neuner) (2009-05-12)
Re: Guidelines for instruction set design? walter@bytecraft.com (Walter Banks) (2009-05-13)
Re: Guidelines for instruction set design? DrDiettrich1@aol.com (Hans-Peter Diettrich) (2009-05-13)
Re: Guidelines for instruction set design? cfc@shell01.TheWorld.com (Chris F Clark) (2009-05-18)
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[1 later articles]
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From: toby <toby@telegraphics.com.au>
Newsgroups: comp.compilers
Date: Sun, 10 May 2009 23:01:28 -0700 (PDT)
Organization: Compilers Central
References: 09-05-020 09-05-034
Keywords: architecture, history
Posted-Date: 12 May 2009 05:05:21 EDT

On May 5, 7:33 pm, George Neuner <gneun...@comcast.net> wrote:
> On Mon, 4 May 2009 02:57:34 -0700 (PDT), cyril.cress...@gmail.com
> wrote:
>
> >About my CPU architecture:
>
> >- 32-bits RISC, implemented in a FPGA
> >- Big Endian
> >- Multipurpose, though it has a MULAC module for signal processing
> >- Word adressable
> ...
> Except for those extra registers it looks a lot like a 68K
> architecture. ...
> I don't know whether there are any open source PDP compilers lying
> about (anybody?),


As it happens I did a (mostly complete) lcc back-end for PDP-11.
http://telegraphics.com.au/svn/lcc_pdp11/trunk/
Discussion @ http://telegraphics.com.au/sw/info/lcc-pdp11.html


There are a number of gotchas in writing machine descriptions for lcc
- which is aimed at reasonably modern CPUs. For example, it is rather
tricky to achieve support for a 32 bit type on PDP-11, which is why my
back-end hasn't done that. :)


Word addressable architectures can also be tricky in lcc. Some byte
operations will simplify the machine description, I think. 68K is one
of its targets.


Source to some freely available 68K compilers is archived here:
http://telegraphics.com.au/svn/smallcnova/trunk/


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