Re: New assembly language instructions to support OO languages?

Glen Herrmannsfeldt <gah@ugcs.caltech.edu>
Mon, 08 Dec 2008 04:05:07 -0700

          From comp.compilers

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[20 earlier articles]
Re: New assembly language instructions to support OO languages? jasen@xnet.co.nz (Jasen Betts) (2008-12-06)
Re: New assembly language instructions to support OO languages? jgd@cix.compulink.co.uk (2008-12-06)
Re: New assembly language instructions to support OO languages? gneuner2@comcast.net (George Neuner) (2008-12-06)
Re: New assembly language instructions to support OO languages? jgd@cix.compulink.co.uk (2008-12-07)
Re: New assembly language instructions to support OO languages? rpw3@rpw3.org (2008-12-08)
Re: New assembly language instructions to support OO languages? torbenm@pc-003.diku.dk (2008-12-08)
Re: New assembly language instructions to support OO languages? gah@ugcs.caltech.edu (Glen Herrmannsfeldt) (2008-12-08)
Re: New assembly language instructions to support OO languages? bowes.brad@gmail.com (Brad) (2008-12-08)
Re: New assembly language instructions to support OO languages? cfc@shell01.TheWorld.com (Chris F Clark) (2008-12-08)
Re: New assembly language instructions to support OO languages? gneuner2@comcast.net (George Neuner) (2008-12-09)
Re: New assembly language instructions to support OO languages? jasen@xnet.co.nz (Jasen Betts) (2008-12-09)
Re: New assembly language instructions to support OO languages? efeustel@hughes.net (Edward Feustel) (2008-12-09)
Re: New assembly language instructions to support OO languages? gah@ugcs.caltech.edu (Glen Herrmannsfeldt) (2008-12-09)
[8 later articles]
| List of all articles for this month |

From: Glen Herrmannsfeldt <gah@ugcs.caltech.edu>
Newsgroups: comp.compilers,comp.arch
Date: Mon, 08 Dec 2008 04:05:07 -0700
Organization: Aioe.org NNTP Server
References: 08-12-025 08-12-039 08-12-042
Keywords: architecture, history, comment
Posted-Date: 08 Dec 2008 07:20:23 EST

George Neuner wrote:
(snip)


> The problem wasn't segmentation per se, but using segmentation as the
> _only_ isolation mechanism ... and the segment limits were too small.
> Using segments+paging in 32-bit mode on the 386 and 486 was fun. The
> Pentium and follow-ons reduced the descriptor cache to just 2 entries
> and made general switching of segments painful.


I have heard rumors about a descriptor cache but I never found
anything about one in any intel documentation. (I did look.)


Are there processors that will check if the selector is the same
as the current selector won't reload the descriptor? I don't
even remember seeing that, but it wouldn't seem hard.


Otherwise, even a small descriptor cache could speed up code
using multiple segments by a large factor.


-- glen
[I never saw an x86 with any sort of performance boost for segments, not
even noticing that you were reloading the same selector. -John]


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