Re: Burroughs/Unisys architecture, was New assembly language instructions to support OO languages?

David W Schroth schrieb:


> The system I work on is both segmented and paged. The Page Table
> (note singular) consumes only a small fraction of memory. Being a
> global Page Table, there is no penalty incurred when switching
> threads.


How does your system avoid an performance loss of 50% or more, when all
memory references go through an address mapping table that again resides
in memory?


> The time to load a segment register is a few cycles, and
> doesn't seem to normally impact performance.
>
> I can't make any sense of your last sentence no matter how I try.


While a small page table can reside in a separate MMU, a limited
number of segment registers or descriptors in a fixed-size memory area
doesn't make much sense to me. How does your model differ from
multi-level indirect references, with regards to execution speed?
What's the benefit of using segment registers, instead of using base
addresses in any other address register?


DoDi

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