Re: Instruction pipe line delay?

Bill Cox <>
Sat, 29 Nov 2008 20:41:51 -0800

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Instruction pipe line delay? (2008-11-28)
Re: Instruction pipe line delay? (Bill Cox) (2008-11-29)
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From: Bill Cox <>
Newsgroups: comp.compilers
Date: Sat, 29 Nov 2008 20:41:51 -0800
Organization: at&t
References: 08-11-139
Keywords: architecture, optimize
Posted-Date: 01 Dec 2008 06:59:56 EST wrote:

As I remember it, the MIPS port of gcc deos some of this - a single
delay slot following a brenahc, I believe.

If that doesn't help, I'd suggest post-processing the assembler code
with a peephole optimizer. After each non-delay ALU instruction, it
would look ahead for one or two legitimate instructions to propagate
backwards into the delay slot. For branch instructions, you look
backwards for one or two instructions to fill the delay slots with.

There *are* instructions which can be used to fill the delay slots,
aren't there? ALU instructions not involving any of the registers
mentioned in the first instruction, for example?


> We got a "embedded" processor which has one delay slot for any
> internal ALU operations and two delay slots for branch and memory load
> instructions, see below example. This is due to hardware throughput
> requirements. And its resonably easy to schedule instructions to
> minimize NOPs when we are doing assembler codes.

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