Re: Superscalars and instruction scheduling

Ricardo Nabinger Sanchez <rnsanchez@wait4.org>
Mon, 17 Nov 2008 01:52:50 -0700

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Related articles
Superscalars and instruction scheduling pertti.kellomaki@tut.fi (Pertti Kellomaki) (2008-11-13)
Re: Superscalars and instruction scheduling rnsanchez@wait4.org (Ricardo Nabinger Sanchez) (2008-11-17)
Re: Superscalars and instruction scheduling SidTouati@inria.fr (Sid Touati) (2008-11-18)
Re: Superscalars and instruction scheduling mayan@bestweb.net (Mayan Moudgill) (2009-02-28)
Re: Superscalars and instruction scheduling SidTouati@inria.fr (Touati Sid) (2009-03-04)
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From: Ricardo Nabinger Sanchez <rnsanchez@wait4.org>
Newsgroups: comp.compilers
Date: Mon, 17 Nov 2008 01:52:50 -0700
Organization: SYS_WAIT4
References: 08-11-053
Keywords: architecture, performance
Posted-Date: 17 Nov 2008 08:25:50 EST

Hello Pertti,


On Thu, 13 Nov 2008 15:04:08 +0200
Pertti Kellomaki <pertti.kellomaki@tut.fi> wrote:


> Googling for "superscalar instruction scheduling performance" gives
> hits to fairly old papers. Does anyone know how important (if at all)
> instruction scheduling is for getting good performance out of modern
> superscalar processors?


Maybe you're looking for papers on cycle-accurate simulation of
processors. If those are not useful, at least they will provide you
with pointers to (hopefully) what you really want.


Regards.


--
Ricardo Nabinger Sanchez http://rnsanchez.wait4.org/
    "Left to themselves, things tend to go from bad to worse."


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