Re: Software Pipelining

kamal <kamalpr@hp.com>
Wed, 10 Sep 2008 21:15:35 -0700 (PDT)

          From comp.compilers
Related articles
Software Pipelining plfriko@yahoo.de (Tim Frink) (2008-08-26)
Re:Software Pipelining Jatin_Bhateja@mentor.com (Jatin Bhateja) (2008-08-28)
Re:Software Pipelining plfriko@yahoo.de (Tim Frink) (2008-08-28)
Re: Software Pipelining pertti.kellomaki@tut.fi (Pertti Kellomaki) (2008-08-29)
Re: Software Pipelining mr.neeraj@gmail.com (Neeraj Goel) (2008-09-02)
Re: Software Pipelining sidtouati@inria.fr (Touati Sid) (2008-09-08)
Re: Software Pipelining kamalpr@hp.com (kamal) (2008-09-10)
Re: Software Pipelining johnhull2008@gmail.com (johnhull2008) (2008-09-11)
Re: Software Pipelining plfriko@yahoo.de (Tim Frink) (2008-09-16)
Re: Software Pipelining plfriko@yahoo.de (Tim Frink) (2008-09-16)
Re: Software Pipelining pertti.kellomaki@tut.fi (Pertti Kellomaki) (2008-09-17)
Re: Software Pipelining cdg@nullstone.com (Christopher Glaeser) (2008-09-21)
Re: Software Pipelining armelasselin@hotmail.com (Armel) (2008-09-24)
[2 later articles]
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From: kamal <kamalpr@hp.com>
Newsgroups: comp.compilers
Date: Wed, 10 Sep 2008 21:15:35 -0700 (PDT)
Organization: Compilers Central
References: 08-08-072 08-08-086 08-08-092
Keywords: code, optimize
Posted-Date: 13 Sep 2008 11:54:01 EDT

On Aug 29, 1:51 am, Tim Frink <plfr...@yahoo.de> wrote:
> On Thu, 28 Aug 2008 11:49:49 +0530, Jatin Bhateja wrote:
> > It's a combination of loop unrolling and instruction scheduling. e.g
>
> Thank you, but I know how software pipelining is working. :-)
>
> My question was if also a significant performance increase for RISC
> architectures with a restricted number of functional units can be
> expected when software pipelining is applied.


You need more than 1 functional unit to take advantage of pipelining.
Be it RISC or VLIW instruction format, that has no bearing on how many
functional units a processor can have,


The itanium processor has a RISC instruction format, and it has a
notion of an EPIC (explicitly parallel instruction) bundle. The
compiler will have to generate a bundle wherein multiple instructions
will be handed to the processor and scheduled for parallel execution
and it will yield a good performance if each of those instructions can
utilize different functional units at the same time.


> And if profiling might be exploited here.


I didn't get you there i.e. profiling doesn't seem related to
pipelining as described above.


regards
-kamal


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