Software Pipelining

Tim Frink <>
26 Aug 2008 14:57:06 GMT

          From comp.compilers

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From: Tim Frink <>
Newsgroups: comp.compilers
Date: 26 Aug 2008 14:57:06 GMT
Organization: Compilers Central
Keywords: optimize, architecture, question
Posted-Date: 26 Aug 2008 23:33:35 EDT


Software pipelining is a technique to reorder loops to achieve more
parallelism at the instruction level. I was wondering if this
optimization is mainly beneficial for processors that have multiple
functional units like VLIWs, or can significant performance
improvements be also achieved for RISC processors with a restricted
number of functional unis like just two 4-stage pipelines?

I was also wondering if software pipelining can benefit from profiling
information, i.e. can the knowledge about frequently executed paths be
exploited for a better pipelining? Do you know any successful


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