|[5 earlier articles]|
|Re: State of the Art firstname.lastname@example.org (Aleksey Demakov) (2008-07-23)|
|Re: State of the Art cfc@shell01.TheWorld.com (Chris F Clark) (2008-07-22)|
|Re: State of the Art email@example.com (2008-07-23)|
|Re: State of the Art firstname.lastname@example.org (Aaron Gray) (2008-07-24)|
|Re: State of the Art email@example.com (Tony Finch) (2008-07-25)|
|Re: State of the Art firstname.lastname@example.org (johnhull2008) (2008-07-28)|
|Re: State of the Art email@example.com (kamal) (2008-07-28)|
|Re: State of the Art firstname.lastname@example.org (Matt Luckman) (2008-07-29)|
|Re: State of the Art email@example.com (2008-08-03)|
|Date:||Mon, 28 Jul 2008 04:05:16 -0700 (PDT)|
|Posted-Date:||28 Jul 2008 09:49:24 EDT|
On Jul 18, 7:40 pm, Peter <peter.deus...@fokus.fraunhofer.de> wrote:
> Hi all,
> I havn't worked in compiler construction and programming languages for
> some years, but now I have a chance to return to this area. I would
> like to find out what happened while I was absent.
can you put a lid on how long you were absent?
> So, let me ask the following questions:
> - In your opinion, what are the greatest advances in compiler
> construction in the last ten years?
some posters [incl. their authors] referred to parsing techniques (PEG/
IMO, Java came in, -then its lack of performance brought up JIT/
hotspot editors/dynamic optimization etc. I haven't seen a technique
come up that improves generated code speed significantly. Most changes
I see in the code base are a reaction to customer input/language
Major changes in compiler optimization (at the back-end) are
invariably driven by changes in processor micro-architecture. So,
tracking architectural changes is probably a good way to locate
changes in compiler back-end technique.
In that regard, POWER archiecture from IBM shifted many optimixations
to h/w via on-chip scheduler/branch-miss prediction. Itanium OTOH
shifted optimizations to s/w. Itanium has a concept of instruction
bundles, which are taken advantage of by the backend to schedule
instructions in parallel on different functional units. In general,
new/emerging changes to hw include :-
-multi core (coz we are hitting moore;s law)
> - What are the most important current trends?
the above 3 issues should be the major drivers [if you depend on
processor roadmaps as a hint]
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