|instruction bundling (scheduling?) email@example.com (kphillips) (2008-04-04)|
|Re: instruction bundling (scheduling?) firstname.lastname@example.org (2008-04-06)|
|Re: instruction bundling (scheduling?) email@example.com (kphillips) (2008-04-09)|
|Re: instruction bundling (scheduling?) firstname.lastname@example.org (2008-04-13)|
|Re: instruction bundling (scheduling?) email@example.com (IndianTechie) (2008-04-14)|
|Re: instruction bundling (scheduling?) firstname.lastname@example.org (kphillips) (2008-04-15)|
|Re: instruction bundling (scheduling?) SidTouati@inria.fr (Sid Touati) (2008-04-22)|
|Date:||Fri, 4 Apr 2008 09:27:22 -0700 (PDT)|
|Posted-Date:||06 Apr 2008 01:16:58 EDT|
I'm currently experimenting with compiler writing and have so far
produced assembly code with basic-block register allocation (using
liveness analysis). I have access to an Itanium machine so I'm now
generating IA-64 assembly, however none of the instructions are being
bundled yet (producing explicit stops at the moment).
I have the following two queries:
1. All list scheduling I've seen deal with latency. What I require is
using constraints in choosing instructions for each bundle. Does this
still fall under the 'instruction scheduling' umbrella, or is it
simply constraint programming? The only sources specific to Itanium
use advanced techniques (no doubt!).
2. Since register allocation uses liveness properties to re-use
registers, it counter-acts the parallelism in instruction bundling.
a. If I remove the liveness analysis, then spill code will have to be
added, increasing the overall cycle length and reducing performance.
b. if on the other hand, register allocation is done after scheduling,
if spill code is still needed then (somehow?), the whole block must be
There are many academic literature on this subject, but none deals
with this at this level of simplicity (basic block) level as far as
I'm concerned. Once again I'd like to thank you for the current and
past suggestions, your assistance has been extremely useful.
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