Re: Pitfalls in interference graph ?

parthaspanda22@gmail.com
Wed, 24 Oct 2007 11:26:17 -0700

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Re: Pitfalls in interference graph ? jeremy.wright@microfocus.com (Jeremy Wright) (2007-10-02)
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From: parthaspanda22@gmail.com
Newsgroups: comp.compilers
Date: Wed, 24 Oct 2007 11:26:17 -0700
Organization: Compilers Central
References: 07-09-104
Keywords: registers
Posted-Date: 24 Oct 2007 17:16:22 EDT

> >I am trying to implement Briggs Optimistic register>allocator after
> >reading the the thesis written by Preston Briggs.


At optimization level 0, you may want not to
iterate like Briggs' or Chaitin's algorithm would.
Typically, a production compiler uses a quick
and dirty register allocator that uses coloring
and an interference graph, but it doesnt iterate.


> >Now for building the interference graph what other>than register pairs
> >is there any other issues that one has to look out> for?


Have you considered the case when virtual registers
are live upon entry to an exception handler?


Sincerely.



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