Call for Papers: RAAW-2 (Chicago, Dec 2007)

Mohamed Zahran <>
Tue, 21 Aug 2007 16:22:08 -0000

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Call for Papers: RAAW-2 (Chicago, Dec 2007) (Mohamed Zahran) (2007-08-21)
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From: Mohamed Zahran <>
Newsgroups: comp.compilers
Date: Tue, 21 Aug 2007 16:22:08 -0000
Organization: Compilers Central
Keywords: CFP, conference, architecture
Posted-Date: 21 Aug 2007 22:29:52 EDT


To be held in conjunction with the
The 40th Annual IEEE/ACM International Symposium on Microarchitecture
(MICRO), 2007
Chicago, Illinois, USA

Workshop Theme

The tremendous advances in process technology provide architects and
microarchitects with many interesting opportunities for making use of
the huge transistor budget to enhance performance and increase
throughput. However, the complexity of software applications and
system software presents a challenging problem. The varying
requirements of the different applications running on a single
machine, as well as the changing behavior of a single application
during its lifetime, make choosing a suitable general purpose
architecture a big challenge.

This raises the need for an architecture that can adapt to the
different requirements of the applications. The power consumption
limits and the growing importance of reliability further add to the
appeal of such adaptive architectures.

The Reconfigurable and Adaptive Architecture Workshop provides a high-
quality forum for computer scientists and engineers to present their
latest research findings in the rapidly evolving field of
reconfigurable and adaptive architectures.

Submission Topics

Topics of interest include, but are not limited to:

        * High performance adaptive and reconfigurable architectures
        * Power-Aware and Thermal-Aware architectures
        * Adaptive architectures for enhanced hardware reliability
        * Compilation techniques for adaptive and reconfigurable
        * Dynamic compilation and runtime execution environments
        * Heterogeneous multiprocessing on a chip
        * Reconfigurable interconnection
        * Hardware/software trade-offs
        * Novel architectures and micro-architectures
        * Reconfigurable embedded computing systems
        * Memory management techniques
        * Static and dynamic profiling techniques
        * Program phase detection and exploitation techniques
        * Hardware acceleration through reconfiguration
        * Integration of FPGAs with microprocessors

Submission Guidelines

The Program Committee invites authors to submit papers up to 5000
words in length, describing original, unpublished recent work related
to the workshop theme. Submission must be in pdf format and emailed
to The submission should include the contact
person's email address on the front page.

The selected papers will be considered for publication in a special
theme issue of JILP. At least one of the author(s) of an accepted
paper is expected to register for the workshop and present the paper.

Important Deadlines
Paper Submission: September 18, 2007

Acceptance Notification: October 26, 2007

Final version of papers: November 12, 2007

Aneesh Aggarwal
Electrical and Computer Engineering
SUNY Binghamton

Pradip Bose
IBM T. J. Watson Research Center

Mohamed Zahran
Electrical Engineering
City University of New York

Program Committee

Bryan Black (AMD)
Alper Buyuktosunoglu (IBM)
Joel Emer (Intel)
Onur Mutlu (Microsoft)
Eric Rotenberg (NCSU)
Rajiv Gupta (UCR)
Scott Mahlke (UMich)
Amir Roth (UPenn)

Contact Us at

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