|Simple retargetable compiler (maybe only local optimizations) email@example.com (Uncle Noah) (2006-02-11)|
|Re: Simple retargetable compiler (maybe only local optimizations) firstname.lastname@example.org (2006-02-14)|
|Re: Simple retargetable compiler (maybe only local optimizations) email@example.com (toby) (2006-02-17)|
|From:||"Uncle Noah" <firstname.lastname@example.org>|
|Date:||11 Feb 2006 14:04:41 -0500|
|Posted-Date:||11 Feb 2006 14:04:41 EST|
I have been looking for some time for an easily (not GCC!) retargetable
compiler, generating assembly code for RISC processor ISAs from ANSI C.
This seems to be utopic since in most attempts the specification for
the target processor is tightly integrated in the code generator (e.g.
AST->IR->assembly). Since this is a very difficult problem in practice,
we can exclude some of the hard stuff. Anyway, these are the
1. Compact (not obfuscated though!) machine description language.
2. Single file machine descriptions.
3. Support for simple register allocation (not necessarily Chaitin
4. No (global) optimizations.
The latter is very important; I'm interested in generating correct code
for different instruction sets, BUT don't care about optimizations. If
it look ugly, I will deal with it later.
Any suggestions? LCC looks nice and jackcc has some nice options
(http://jackcc.sourceforge.net) but neither scores all 4 requirements.
Return to the
Search the comp.compilers archives again.