|VHDL Simulator firstname.lastname@example.org (Soma Sekhar) (2006-02-02)|
|Re: VHDL Simulator email@example.com (Uncle Noah) (2006-02-03)|
|Re: VHDL Simulator firstname.lastname@example.org (john Doef) (2006-02-03)|
|Re: VHDL Simulator email@example.com (Mayank) (2006-02-03)|
|Re: VHDL Simulator firstname.lastname@example.org (glen herrmannsfeldt) (2006-02-06)|
|From:||glen herrmannsfeldt <email@example.com>|
|Date:||6 Feb 2006 00:07:14 -0500|
|Posted-Date:||06 Feb 2006 00:07:14 EST|
> Few VHDL simulators: Cadence's NC-Sim, Mentor's Modelsim and ghdl (GNU
> project). Google shall help you out, in case you need more details.
> I personally prefer NC-Sim because of capacity and performance reasons.
> Soma Sekhar wrote:
>>If anyone is doing projects on VHDL, please help me,
>>How to simulate VHDL codes, and what is the tool used ??
Also, Altera and Xilinx supply free tools to use to design logic
for their chips. These include a simulator.
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