|help_needed in bison/yacc email@example.com (vicky) (2005-05-02)|
|Re: help_needed in bison/yacc Meyer-Eltz@t-online.de (Detlef Meyer-Eltz) (2005-05-02)|
|Re: help_needed in bison/yacc Brian.Inglis@SystematicSW.ab.ca (Brian Inglis) (2005-05-06)|
|Re: help_needed in bison/yacc firstname.lastname@example.org (Clint Olsen) (2005-06-10)|
|From:||Clint Olsen <email@example.com>|
|Date:||10 Jun 2005 22:14:22 -0400|
|Keywords:||yacc, practice, parse|
|Posted-Date:||10 Jun 2005 22:14:22 EDT|
On 2005-05-02, vicky <firstname.lastname@example.org> wrote:
> my input is verilog code, and i need to convert ternary expressions
> into if-else statements.
> please tell me if it is possible using Flex/Bison (i.e. pls tell me
> how to create interperter using flex/bison).
> All i wanted to say is, i don't want to take pain for writing grammer
> for whole verilog code. i just want to make changes in turnary
> expression. i.e. want a small script to change turnary expression into
> if-else statement. pls help.
The verilog language itself is very large. I would avoid trying to parse
the whole language unless you can steal a good grammar from someone. You
would be better off writing a scanning kind of tool in Perl to do what you
want. The problem is that unless you are only going to handle simple
sub-expressions of the ternary, it could get ugly very fast. And you'll
need something that can create new symbols which won't collide with any
currently in your Verilog model because if/then statements must have a
valid left-hand-side which is the target of an assignment. To be more
specific would be difficult without knowing how complex the Verilog source
is that you're trying to transform.
Return to the
Search the comp.compilers archives again.