|[6 earlier articles]|
|Re: CFGs vs. "declare variable before use" firstname.lastname@example.org (glen herrmannsfeldt) (2005-05-31)|
|Re: CFGs vs. "declare variable before use" email@example.com (Edsko de Vries) (2005-06-02)|
|Re: CFGs vs. "declare variable before use" cfc@shell01.TheWorld.com (Chris F Clark) (2005-06-02)|
|Re: CFGs vs. "declare variable before use" firstname.lastname@example.org (glen herrmannsfeldt) (2005-06-04)|
|Re: CFGs vs. "declare variable before use" email@example.com (mefrill) (2005-06-04)|
|Re: CFGs vs. "declare variable before use" firstname.lastname@example.org (Swapnajit Mittra) (2005-06-08)|
|Re: CFGs vs. "declare variable before use" email@example.com (2005-06-08)|
|Date:||8 Jun 2005 22:31:14 -0400|
|References:||05-05-21605-05-231 05-06-021 05-06-023 05-06-040|
|Posted-Date:||08 Jun 2005 22:31:14 EDT|
This should be clarified. An undeclared identifier creates an implicit
net declaration only if it appears in certain specific contexts: an
instance port expression, or in Verilog-2001, the LHS of a continuous
assignment. In other contexts, such as within procedural code, a
reference to an undeclared identifier is simply an error.
After an implicit net declaration, a later explicit declaration would
indeed be an illegal redeclaration of the identifier.
So yes, it is illegal to declare a variable or net after its use.
One oddity occurs with module ports. A Verilog-1995 port declaration
includes two declarations: the declaration as a port, and the
declaration as a net or variable. If there is no declaration as a net
or variable, then it is implicitly declared as a net. In Verilog-XL
and any simulator that matches it, you can have the port declaration,
then uses of the identifier, then later a declaration of the identifier
as a net or variable. This isn't really a use before declaration,
since the port part of the declaration appeared before the use.
However, the identifier has not been fully declared at that point.
Functions are a special case. Verilog-XL allows the use of a simple
name for a function when it is actually a hierarchical reference to the
function. This allows declaring a set of shared functions in a
top-level module and referring to them from anywhere, without having to
use a hierarchical name. In effect, all function names are processed
as if they were hierarchical function names. So if you have a call to
a function that is not declared yet, this is OK, because it is treated
as a hierarchical name. Then during the upward search to find the
function, if it is declared in the local module, that will be found
first. This has the effect of allowing functions to be declared after
their use. I don't think that this treatment of functions is specified
in the IEEE standard, but since Verilog-XL does it, it is de facto
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