|Compiler positions available for week ending July 18 firstname.lastname@example.org (2004-07-18)|
|Compiler positions available for week ending July 18 email@example.com (comp.compilers) (2010-07-18)|
|Compiler positions available for week ending July 18 firstname.lastname@example.org (1993-07-18)|
|Compiler positions available for week ending July 18 email@example.com (1999-07-19)|
|Date:||18 Jul 2004 09:42:42 -0400|
|Posted-Date:||18 Jul 2004 09:42:42 EDT|
This is a digest of ``help wanted'' and ``position available'' messages
received at comp.compilers during the preceding week. Messages must
advertise a position having something to do with compilers and must also
conform to the guidelines periodically posted in misc.jobs.offered.
Positions that remain open may be re-advertised once a month. To respond
to a job offer, send mail to the author of the message. To submit a
message, mail it to firstname.lastname@example.org.
From: "V i d y a P r a v e e n" <email@example.com>
Subject: C-to-RTL position at Poseidon Design Systems, Bangalore
Poseidon Design Systems provides innovative Electronic System Level
(ESL) solutions for embedded system design. Poseidon Design Systems,
India is looking for experienced candidates with the following
Work on an exciting new technology involving a C-to-RTL Compiler.
Your primary responsibility will be in the C-to-RTL compiler. The
work involves implementing new optimizations in the Compiler, and
integrating the Compiler with our other tools/framework. This
Compiler achieves conversion of ANSI C Source code into RTL level VHDL
code for H/W Synthesis. Also, the work includes traditional C Compiler
optimizations involving loop transformations and parallelism related
Experience : 2-6 years
Positions : Senior Member - Technical Staff /
A. Must have been a Technical Manager/Lead Developer/
Developer for a Compiler Development Project.
B. Must have thorough understanding of Compiler
optimizations including High Level Optimizations and
Low Level Machine Specific Optimization techniques.
C. Must have good understanding of Parallelism related
D. Must have experience in a complete development and
deployment cycle of an industry standard C/C++
A. Knowledge of VLIW / SIMD or other parallel machine
architectures will be a plus
B. Knowledge of Hardware Description Languages (VHDL/
Verilog) would be an added advantage
C. Knowledge of synthesis tools and simulators used in
hardware design will be a plus.
Positions are based in Bangalore, India.
Interested candidates, please email your resume to:
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