Re: Code-Covertor from System C to Verilog?

monikatalwar@hotmail.com (Monika Talwar) wrote in message news:04-04-097...
> I'm writing converter -> SystemC to Verilog, Vera & VHDL.
>
> Can any body help me, how to start.


The current version of SystemC is a C++ class library for
simulation/hardware related classes and then free form C++.


Are you looking to (a) implement a functionally correct language to
language translation or (b) implement "synthesizer" of the hardware
implied by a SystemC description to the hardware description languages
such as Verilog ?


Both are quite non trivial;


(a) is doable and is perhaps somewhat more complex than writing a C++
to C converter; you might consider starting with a C++ to C converter
and some how put in a pass that converts the hardware specific class
instances to corresponding verilog, and then change the C converter to
be a Verilog converter (low level C and sequential (i.e., non
parallel) Verilog look pretty much the same so this is the "easy" part
:-).


Another approach to (a) might be to look at source to source language
translator tools such as Semantic Design's DMS, or TXL's TXL. Since
there is a C++ front to these tools you can then focus on the
conversion part of the problem.


(b) is doable but is a much bigger project than (a). to produce
something efficient a relatively narrow subset of the language will
have to be defined. You should look at the synthesis literature and
reconfigurable computing literature.
(http://mesl.ucsd.edu/spark/ is a project that does subset C to VHDL;
http://cag-www.lcs.mit.edu/raw/documents/index.html addresses similar
issues in the compiler)


If this is some sort of a class/degree project you need to scale what
you will attempt down to something that is manageable and interesting.

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