|Def use chain length minimization email@example.com (2003-10-27)|
|RE: Def use chain length minimization firstname.lastname@example.org (Naveen Sharma, Noida) (2003-10-31)|
|From:||"Naveen Sharma, Noida" <email@example.com>|
|Date:||31 Oct 2003 23:03:41 -0500|
|Posted-Date:||31 Oct 2003 23:03:41 EST|
> Can some body point me to any literature on minimizing def-use
> chains so that there is no cache miss between them. In other words can
> load stores be scheduled so that they are close enough of course no
> more closer than the latency of the load.
See this work done in gcc (related to scheduling before regsiter
The basic problem here was that un-restrained load-store
scheduling leads lot of spills during register-alloctaion.
I think this is in a sense related to your problem, although,
you have cache misses in mind.
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