|Machine descriptions for code generation? firstname.lastname@example.org (Evan Lavelle at dot) (2002-10-13)|
|Re: Machine descriptions for code generation? email@example.com (Rainer Leupers) (2002-10-18)|
|Re: Machine descriptions for code generation? "firstname.lastname@example.org"@telenet-ops.be (Gert Goossens) (2002-10-25)|
|Re: Machine descriptions for code generation? email@example.com (Evan Lavelle) (2002-11-06)|
|Re: Machine descriptions for code generation? firstname.lastname@example.org (Gopi Bulusu) (2002-11-08)|
|From:||"Gopi Bulusu" <email@example.com>|
|Date:||8 Nov 2002 11:04:08 -0500|
|Posted-Date:||08 Nov 2002 11:04:08 EST|
"Evan Lavelle" <firstname.lastname@example.org> wrote in message news:02-11-024...
> MDL MDL public-domain? compiler? compiler ILP support?
Here is a Dynamically Targetable Tools Framework from Sankhya:
SMDL Not Yet DTTF/STC Yes
(Available under NDA)
Our framework can support RISC/CISC/VLIW/DSP processors.
We have initial proof-of-concept implementation of a code generator,
assembler, linker (a simple linker) and simulator for MIPS and ARM
processors and all of which use a single model-set of a new processor
to be supported. In addition to MIPS and ARM, we have created machine
models for Hitachi SH3, TI C67X and part of the IA64 instruction set.
With DTTF, when a model is changed there is generally no need to
regenerate or rebuild the tools as the tools can dynamically load
The simulator ssim can simulate multiple processors of different
models simultaneously and these can be interconnected through
(simulated) shared memory etc.
Here are additional pointers:
Gopi Kumar Bulusu
Sankhya Technologies Private Limited
Tel: +91 44 822 7358
Fax: +91 44 822 7357
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