|Machine descriptions for code generation? firstname.lastname@example.org (Evan Lavelle at dot) (2002-10-13)|
|Re: Machine descriptions for code generation? email@example.com (Rainer Leupers) (2002-10-18)|
|Re: Machine descriptions for code generation? "firstname.lastname@example.org"@telenet-ops.be (Gert Goossens) (2002-10-25)|
|Re: Machine descriptions for code generation? email@example.com (Evan Lavelle) (2002-11-06)|
|Re: Machine descriptions for code generation? firstname.lastname@example.org (Gopi Bulusu) (2002-11-08)|
|From:||"Evan Lavelle at dot" <email@example.com>|
|Date:||13 Oct 2002 16:37:06 -0400|
|Organization:||Riverside Machines Ltd.|
|Posted-Date:||13 Oct 2002 16:37:06 EDT|
I'm currently using two different instruction set definitions for the
same machine. One of them defines the instruction set for the hardware
model, and the other is the definition for the instruction-level
simulator, which is used to test the hardware model. I've now got the
problem of adding a third description, for compiler porting.
What I'd really like to do is to standardise on a single
representation of the machine description, so that I can guarantee
that the compiler, simulator, and hardware model are all talking about
the same processor. However, the most important use of the description
would be to simplify compiler porting.
I've done a quick search, and the closest thing I can find to a usable
description language is Zephyr's Lambda-RTL
(http://www.cs.virginia.edu/zephyr/csdl/lrtlindex.html). Can anyone
suggest any alternative descriptions, or does anyone have any
experience, good or bad, of using these descriptions? Ideally, I'd
like to be able to port a usable compiler directly from the
description, but I guess that's just going to be wishful thinking for
the next few years.
[GCC uses RTL fairly successfully, although there's still plenty of
hand work to target a new architecture. -John]
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